US 11,658,062 B2
Air gap spacer formation for nano-scale semiconductor devices
Kangguo Cheng, Schenectady, NY (US); Thomas J. Haigh, Claverack, NY (US); Juntao Li, Cohoes, NY (US); Eric G. Liniger, Sandy Hook, CT (US); Sanjay C. Mehta, Niskayuna, NY (US); Son V. Nguyen, Schenectady, NY (US); Chanro Park, Clifton Park, NY (US); and Tenko Yamashita, Schenectady, NY (US)
Assigned to TESSERA LLC, San Jose, CA (US)
Filed by TESSERA LLC, San Jose, CA (US)
Filed on May 13, 2019, as Appl. No. 16/410,178.
Application 16/410,178 is a division of application No. 15/977,437, filed on May 11, 2018, granted, now 10,418,277.
Application 15/789,416 is a division of application No. 15/232,341, filed on Aug. 9, 2016, granted, now 9,892,961, issued on Feb. 13, 2018.
Application 15/977,437 is a continuation of application No. 15/789,416, filed on Oct. 20, 2017, granted, now 10,115,629, issued on Oct. 30, 2018.
Prior Publication US 2019/0267279 A1, Aug. 29, 2019
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/7682 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02126 (2013.01); H01L 21/02167 (2013.01); H01L 21/02274 (2013.01); H01L 21/76852 (2013.01); H01L 23/528 (2013.01); H01L 23/5329 (2013.01); H01L 29/41775 (2013.01); H01L 29/4991 (2013.01); H01L 29/6653 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device comprising:
a substrate;
a first interconnect level; and
a second interconnect level above the first interconnect level, the second interconnect level comprising:
a first metal line extending in a first direction parallel to the substrate;
a second metal line adjacent to and parallel to the first metal line and extending in the first direction;
an air gap spacer extending in the first direction between the first and second metal lines and extending vertically to a pinch-off region formed in a dielectric capping material, wherein the pinch-off region is formed above a plane comprising top surfaces of the first and second metal lines;
a first self-aligned conductive protective cap on the first metal line;
a second self-aligned conductive protective cap on the second metal line; and
a conformal insulating liner disposed directly on top of a conductive portion of the first and second self-aligned conductive protective caps and on opposing sides of the first and second metal lines adjacent the air gap spacer, the conformal insulating liner being continuous below the air gap spacer,
wherein a lateral distance between the first and second metal lines is in a range from 6 nm to 10 nm, and
wherein a thickness of the conformal insulating liner is in a range from 0.5 nm to less than 5 nm.