US 11,658,027 B2
Method of manufacturing semiconductor device
Takahide Hirasaki, Osaka (JP)
Assigned to SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka (JP)
Filed by SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka (JP)
Filed on Jun. 4, 2021, as Appl. No. 17/338,892.
Claims priority of application No. JP2020-105954 (JP), filed on Jun. 19, 2020.
Prior Publication US 2021/0398806 A1, Dec. 23, 2021
Int. Cl. H01L 21/02 (2006.01)
CPC H01L 21/02458 (2013.01) [H01L 21/0254 (2013.01); H01L 21/02351 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming, on or above a GaN-based semiconductor layer, a first electron beam resist, a second electron beam resist, and a third electron beam resist, at least one of the first electron beam resist and the third electron beam resist containing chlorine;
forming a first opening in the first electron beam resist, a second opening in the second electron beam resist, and a third opening in the third electron beam resist, wherein the first opening exposes a portion of a surface of the semiconductor layer, the second opening is larger in width than the first opening, and the third opening is larger in width than the first opening and smaller in width than the second opening;
forming a film of a shrink agent that covers an upper surface of the third electron beam resist and each of sidewall surfaces of the first opening, the second opening, and the third opening; and
forming, in a state in which the sidewall surfaces are covered by the film of the shrink agent, a Ni film that contacts the semiconductor layer through the first opening.