US 11,657,981 B2
Method and apparatus for compensating for high Thermal Expansion Coefficient mismatch of a stacked device
Marina Zelner, Burlington (CA); Andrew Vladimir Claude Cervin, Oakville (CA); and Edward Horne, Burlington (CA)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Sep. 30, 2020, as Appl. No. 17/38,062.
Application 17/038,062 is a division of application No. 15/901,468, filed on Feb. 21, 2018, granted, now 10,923,286.
Prior Publication US 2021/0012970 A1, Jan. 14, 2021
Int. Cl. H01L 21/00 (2006.01); H01G 7/06 (2006.01); H01L 21/3115 (2006.01); H01L 23/373 (2006.01); H01L 49/02 (2006.01)
CPC H01G 7/06 (2013.01) [H01L 21/3115 (2013.01); H01L 23/3735 (2013.01); H01L 28/55 (2013.01); H01L 28/91 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for fabricating a capacitor, the method comprising:
providing a first silicon dioxide layer on a substrate;
depositing a modifier layer on the first silicon dioxide layer;
depositing a second silicon dioxide layer on the modifier layer to form a multilayer initial oxide;
annealing the multilayer initial oxide resulting in an annealed multilayer initial oxide, wherein the annealing causes diffusion of modifier species from the modifier layer into the first and second silicon dioxide layers and results in amorphous polysilicates, the first and second silicon dioxide layers having thicknesses that prevent the diffusion of the modifier species from reaching top and bottom interfaces of the annealed multilayer initial oxide, wherein the annealed multilayer initial oxide mitigates delamination;
depositing a first electrode layer on the annealed multilayer initial oxide;
depositing a dielectric layer on the first electrode layer; and
depositing a second electrode layer on the dielectric layer.