US 11,657,892 B1
Repairable latch array
Joel Thornton Irby, Austin, TX (US); and Grady L. Giles, Austin, TX (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/561,115.
Int. Cl. G11C 7/10 (2006.01); G11C 29/44 (2006.01); G11C 29/12 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/4401 (2013.01) [G11C 7/106 (2013.01); G11C 7/1012 (2013.01); G11C 7/1036 (2013.01); G11C 7/1087 (2013.01); G11C 29/1201 (2013.01); G11C 29/46 (2013.01); G11C 2029/1202 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a latch array comprising:
a plurality of latches logically configured in rows and columns;
a plurality of repair latches operatively coupled to the plurality of latches;
latch array built in self-test and repair logic operatively coupled to the plurality of latches and operative to:
configure a plurality of latches that are in a column as at least one serial test shift register;
detect at least one defective latch of the plurality of latches based on applied test data; and
select at least one repair latch in response to detection of the at least one defective latch.