US 11,657,891 B2
Error recovery operations
Guang Hu, Mountain View, CA (US); Ting Luo, Santa Clara, CA (US); and Chun Sum Yueng, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 13, 2022, as Appl. No. 17/743,989.
Application 17/743,989 is a continuation of application No. 17/122,864, filed on Dec. 15, 2020, granted, now 11,335,429.
Prior Publication US 2022/0270702 A1, Aug. 25, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/42 (2006.01); G11C 7/20 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 7/20 (2013.01); G11C 29/44 (2013.01)] 20 Claims
OG exemplary drawing
1. A method, comprising:
performing an error recovery operation involving a set of memory cells;
subsequent to performing the error recovery operation, determining whether a data reliability parameter associated with the set of memory cells meets a data reliability criteria; and
in response to determining that the data reliability criteria is less than a threshold data reliability criteria, setting an offset associated with the error recovery operation as a default read voltage for the set of memory cells.