US 11,657,887 B2
Testing bit write operation to a memory array in integrated circuits
Thomas J. Knips, Wappingers Falls, NY (US); Uma Srinivasan, Poughkeepsie, NY (US); Daniel Rodko, Poughkeepsie, NY (US); Matthew Steven Hyde, Wappingers Falls, NY (US); and William V. Huott, Holmes, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 17, 2021, as Appl. No. 17/477,715.
Prior Publication US 2023/0089274 A1, Mar. 23, 2023
Int. Cl. G11C 29/38 (2006.01)
CPC G11C 29/38 (2013.01) 17 Claims
OG exemplary drawing
 
1. A method for testing a circuit, the method comprising:
performing, by a test engine, a test of bit write to a memory, the test comprising:
defining a set of bit write address bit groups and their respective decodes based on a set of input bits from an address to be tested of a memory location, wherein each respective decode comprises a multi-input, multi-output combination that converts a binary code of M input lines into one of N outputs, and wherein the set of input bits are taken from predetermined bit locations in the address;
generating an encoded binary number in a predetermined range of 1 to M based on the set of input bits from the address;
generating, from the encoded binary number, a decoded binary number in a predetermined range of 1 to N;
generating, from a bit pattern of the decoded binary number, a bit mask for the bit groups;
generating, from a bit pattern of the encoded binary number, expect data;
performing a bit write operation comprising a partial write to the address to store a sequence of bits, the sequence of bits selected using a predetermined bit pattern testing algorithm configured to test bit write capability;
reading a content of the address; and
comparing bits selected using the bit mask to the expect data.