US 11,657,875 B2
Semiconductor memory device configured to output write parameter and memory system including the same
Suguru Nishikawa, Osaka (JP); Yoshihisa Kojima, Kawasaki (JP); Riki Suzuki, Yokohama (JP); Masanobu Shirakawa, Chigasaki (JP); and Toshikatsu Hida, Yokohama (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jun. 24, 2022, as Appl. No. 17/849,062.
Application 17/849,062 is a continuation of application No. 17/027,041, filed on Sep. 21, 2020, granted, now 11,410,729.
Application 17/027,041 is a continuation of application No. 16/129,157, filed on Sep. 12, 2018, granted, now 10,818,358, issued on Oct. 27, 2020.
Claims priority of application No. JP2017-183074 (JP), filed on Sep. 22, 2017; and application No. JP2018-033796 (JP), filed on Feb. 27, 2018.
Prior Publication US 2022/0328102 A1, Oct. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01); G11C 29/02 (2006.01); G11C 29/42 (2006.01); G11C 16/32 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01)
CPC G11C 16/10 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/32 (2013.01); G11C 16/349 (2013.01); G11C 16/3459 (2013.01); G11C 16/3495 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 29/42 (2013.01); G11C 11/5671 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory device connectable to a controller, the memory device comprising:
at least a first memory cell configured to be programmed to store data corresponding to a threshold voltage of the first memory cell, the first memory cell being configured to store first data in a case where the threshold voltage of the first memory cell is higher than a second reference voltage; and
a peripheral circuit configured to:
write the first data to the first memory cell in a first programming operation by:
applying a first program voltage to the first memory cell in a plurality of first loops, a level of the first program voltage applied to the first memory cell first in the plurality of first loops being a first initial voltage;
obtaining a value of a first write parameter by comparing the threshold voltage of the first memory cell with a first reference voltage, the first reference voltage being lower than the second reference voltage, the first write parameter including a level of the first program voltage applied to the first memory cell in one of the plurality of first loops; and
verifying that the first data is stored in the first memory cell by comparing the threshold voltage of the first memory cell with the second reference voltage; and
output the value of the first write parameter to the controller.