US 11,657,870 B2
Method and system to balance ground bounce
Hidehiro Fujiwara, Hsin-chu (TW); Hsien-Yu Pan, Hsinchu (TW); Chih-Yu Lin, Taichung (TW); Yen-Huei Chen, Jhudong Township (TW); and Wei-Chang Zhao, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 21, 2021, as Appl. No. 17/381,234.
Application 17/381,234 is a continuation of application No. 16/659,055, filed on Oct. 21, 2019, granted, now 11,074,966.
Claims priority of provisional application 62/753,749, filed on Oct. 31, 2018.
Prior Publication US 2021/0350849 A1, Nov. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 11/419 (2006.01); H01L 27/02 (2006.01); H01L 27/11 (2006.01); G11C 11/412 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/412 (2013.01); H01L 27/0207 (2013.01); H01L 27/1104 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory cell in a memory device, comprising:
a write port comprising:
a storage unit comprising a first cross-coupled inverter connected to a second cross-coupled inverter, wherein the first and the second cross-coupled inverters are connected between a first power source signal line and a second power source signal line;
a first pass transistor having a first terminal connected to a write bit line (WBL) signal line, a second terminal connected to the first cross-coupled inverter, and a first gate connected to a write word line (WWL) signal line;
a second pass transistor having a third terminal connected to a write bit line bar (WBLB) signal line, a fourth terminal connected to the second cross-coupled inverter, and a second gate connected to the WWL signal line; and
a first local interconnect line in an interconnect layer connected to the first power source signal line; and
a read port comprising:
a transistor connected to the storage unit in the write port and to the first power source signal line;
a third pass transistor having a fifth terminal connected to a read bit line (RBL) signal line, a sixth terminal connected to the transistor, and a third gate connected to a read word line (RWL) signal line; and
a second local interconnect line in the interconnect layer connected to the first power source signal line, wherein:
the second local interconnect line in the read port is separate from the first local interconnect line in the write port;
the WWL signal line, the WBL signal line, the WBLB signal line, the RWL signal line, the RBL signal line, the first power source signal line, and the second power source signal line are formed in a conductive layer; and
a layout of the conductive layer from a first edge of the memory cell to an opposite second edge of the memory cell comprises: the WWL signal line-the first power source signal line-the WBL signal line-the second power source signal line-the WBLB signal line-the first power source signal line-the WWL signal line-the first power source signal line-the RBL signal line-the RWL signal line.