US 11,657,863 B2
Memory array test structure and method of forming the same
Meng-Han Lin, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 9, 2021, as Appl. No. 17/397,414.
Claims priority of provisional application 63/211,765, filed on Jun. 17, 2021.
Prior Publication US 2022/0406350 A1, Dec. 22, 2022
Int. Cl. G11C 8/08 (2006.01); G11C 29/50 (2006.01); G11C 29/02 (2006.01); H01L 21/822 (2006.01); G11C 29/12 (2006.01)
CPC G11C 8/08 (2013.01) [G11C 29/025 (2013.01); G11C 29/12 (2013.01); G11C 29/50 (2013.01); H01L 21/8221 (2013.01); G11C 2029/1202 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory array comprising:
a first word line over a semiconductor substrate, wherein a longitudinal axis of the first word line extends in a first direction;
a second word line over the first word line in a second direction perpendicular to a major surface of the semiconductor substrate, wherein a longitudinal axis of the second word line extends in the first direction;
a memory film contacting the first word line and the second word line;
an oxide semiconductor (OS) layer contacting a first source line and a first bit line, wherein the memory film is between the OS layer and each of the first word line and the second word line; and
a test structure over the first word line and the second word line, the test structure comprising a first conductive line electrically coupling the first word line to the second word line, wherein a longitudinal axis of the first conductive line extends in the first direction.