US 11,657,858 B2
Nonvolatile memory devices including memory planes and memory systems including the same
Hyun-Jin Kim, Hwaseong-si (KR); Chung-Ho Yu, Hwaseong-si (KR); Yong-Kyu Lee, Hwaseong-si (KR); and Jae-Yong Jeong, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 3, 2021, as Appl. No. 17/338,097.
Application 17/338,097 is a continuation in part of application No. 16/432,959, filed on Jun. 6, 2019, granted, now 11,037,626.
Claims priority of application No. 10-2018-0150016 (KR), filed on Nov. 28, 2018.
Prior Publication US 2021/0295884 A1, Sep. 23, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 7/1012 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile memory device comprising:
a memory cell region including a first metal pad;
a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
a plurality of memory planes comprising a plurality of page buffer circuits and a plurality of memory cell arrays including nonvolatile memory cells stacked in a vertical direction to form cell strings, wherein the plurality of page buffer circuits are arranged in the peripheral circuit region, the plurality of memory cell arrays are arranged in the memory cell region, and wherein each of the plurality of page buffer circuits is connected through bitlines to ones of the nonvolatile memory cells included in a respective memory cell array of the plurality of memory cell arrays; and
a plurality of plane-dedicated pad sets connected to the plurality of page buffer circuits through a plurality of data paths such that each of the plurality of plane-dedicated pad sets is connected dedicatedly to a respective page buffer circuit of the plurality of page buffer circuits,
wherein each of the plurality of plane-dedicated pad sets comprises a plurality of data pads connected dedicatedly to the respective page buffer circuit, and
wherein the nonvolatile memory device is configured to receive commands and addresses from a memory controller through ones of the plurality of data pads included in at least one of the plurality of plane-dedicated pad sets.