US 11,657,760 B2
Light emission driver and display device having the same
Jun Hyun Park, Yongin-si (KR); Bon Yong Koo, Yongin-si (KR); Yu Jin Lee, Yongin-si (KR); and Kyung Hoon Chung, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Jun. 1, 2020, as Appl. No. 16/889,606.
Claims priority of application No. 10-2019-0110141 (KR), filed on Sep. 5, 2019.
Prior Publication US 2021/0074215 A1, Mar. 11, 2021
Int. Cl. G09G 3/3258 (2016.01); G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01)
CPC G09G 3/3258 (2013.01) [G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0252 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A light emission driver comprising:
a plurality of stages configured to output a light emission control signal,
wherein each of the stages comprises:
an input circuit comprising a first input terminal, a second input terminal, and a third input terminal, wherein the input circuit is configured to control voltages of a first node and a second node in response to first and second clock signals;
an output circuit configured to supply a voltage of a first power or a voltage of a second power to an output terminal in response to a voltage of a third node and a voltage of a fourth node;
a first signal processor connected to a fifth node electrically connecting the second node and the fourth node to each other, and configured to control the voltage of the fourth node based on the second clock signal supplied to the third input terminal and a voltage of the fifth node;
a second signal processor configured to control the voltage of the fourth node in response to the voltage of the third node;
a first stabilizer electrically connected between the input circuit and the output circuit, and configured to limit a voltage drop of the first node and the second node; and
a second stabilizer configured to control an electrical connection between the third node and the first node in response to the voltage of the fourth node and the second clock signal supplied to the third input terminal,
wherein the second stabilizer comprises a first transistor having a first electrode connected to the fourth node and a gate electrode connected to the third input terminal and a second transistor connected between the first node and the third node and having a gate electrode connected to a second electrode of the first transistor,
wherein the second stabilizer is configured to disconnect the electrical connection between the first node and the third node in response to the second clock signal supplied to the third input terminal and the voltage of the fourth node, in a period in which the light emission control signal has a gate on level, and
wherein the electrical connection between the first node and the third node is disconnected as the second transistor is turned off by the voltage of the fourth node of the gate off level.