US 11,657,262 B2
Processing matrix operations for rate limited systems
Matthew Raja Khoury, Cambridge, MA (US); Rumen Rumenov Dangovski, Cambridge, MA (US); Longwu Ou, Cambridge, MA (US); Yichen Shen, Cambridge, MA (US); and Li Jing, Cambridge, MA (US)
Assigned to Lightelligence, Inc., Boston, MA (US)
Filed by Lightelligence, Inc., Boston, MA (US)
Filed on Nov. 11, 2022, as Appl. No. 17/985,482.
Application 17/985,482 is a continuation of application No. 16/778,495, filed on Jan. 31, 2020, granted, now 11,526,737.
Claims priority of provisional application 62/799,849, filed on Feb. 1, 2019.
Prior Publication US 2023/0077270 A1, Mar. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/063 (2023.01); G06F 17/16 (2006.01); G06N 20/10 (2019.01); G06N 3/08 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 17/16 (2013.01); G06N 3/08 (2013.01); G06N 20/10 (2019.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus for processing data that includes vector element values of an input vector and matrix element values of a model matrix, the apparatus comprising:
a clock module configured to provide a clock signal associated with the data;
a vector-matrix multiplication module configured to receive a set of matrix element values for performing a vector-matrix multiplication, and
a computing subsystem configured to process data based on the clock signal, the processing including:
loading the vector-matrix multiplication module with a core matrix,
computing a plurality of intermediate vectors based on element-wise vector multiplication between different subsets of the vector element values and different respective pre-processing vectors, where the number of cycles of the clock signal used to compute the plurality of intermediate vectors is less than a number of cycles used to load the core matrix, and
multiplying the input vector by the model matrix based on separately multiplying each of the intermediate vectors by the loaded core matrix.