US 11,657,259 B2
Kernel transformation techniques to reduce power consumption of binary input, binary weight in-memory convolutional neural network inference engine
Tung Thanh Hoang, San Jose, CA (US); Won Ho Choi, San Jose, CA (US); and Martin Lueker-Boden, Fremont, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Dec. 20, 2019, as Appl. No. 16/722,580.
Prior Publication US 2021/0192325 A1, Jun. 24, 2021
Int. Cl. G06N 3/04 (2023.01); G06N 3/063 (2023.01); G11C 13/00 (2006.01); G06F 7/523 (2006.01); G11C 11/54 (2006.01); G06N 3/08 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 7/523 (2013.01); G06N 3/04 (2013.01); G11C 11/54 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G06N 3/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A non-volatile memory device, comprising:
a plurality of non-volatile memory cells configured to store a plurality of ternary valued weights of one or more filters of a convolutional neural network, each of the ternary valued weights stored in a pair of memory cells connected to a corresponding pair of word lines and connected on a common bit line;
a register connected to the one or more control circuits and configured to store a number of zero valued weights stored in the memory cells connected along the common bit line; and
one or more control circuits connected to the non-volatile memory cells, the one or more control circuits configured to:
receive a plurality of binary inputs for a layer of a neural network;
convert each of the plurality of binary inputs into a corresponding one of a pair of voltage patterns;
apply the plurality of voltage patterns to the non-volatile memory cells to thereby perform an in-memory multiplication of the plurality of binary inputs with the ternary valued weights;
accumulate results of the in-memory multiplication; and
compensate the accumulated results of the in-memory multiplication based on the number of zero valued weights stored in the memory cells connected along the common bit lines.