US 11,657,203 B2
Multi-phase topology synthesis of a network-on-chip (NoC)
Moez Cherif, Santa Cruz, CA (US); and Benoit de Lescure, Campbell, CA (US)
Assigned to ARTERIS, INC., Campbell, CA (US)
Filed by ARTERIS, INC., Campbell, CA (US)
Filed on Dec. 9, 2020, as Appl. No. 17/116,344.
Application 17/116,344 is a continuation in part of application No. 16/728,335, filed on Dec. 27, 2019, granted, now 11,121,933.
Prior Publication US 2021/0200928 A1, Jul. 1, 2021
Int. Cl. G06F 30/392 (2020.01); G06F 15/78 (2006.01); G06F 115/02 (2020.01); G06F 111/20 (2020.01); G06F 111/04 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 15/7807 (2013.01); G06F 15/7825 (2013.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01); G06F 2115/02 (2020.01)] 10 Claims
OG exemplary drawing
1. A method for generation of a network, the method comprising:
receiving constraints for the network;
executing topology synthesis using the constraints to generate an abstract network as a solution for implementation of the network, wherein the abstract network includes abstract network elements representing simplified real elements;
generating, using the abstract network, a real network representation of the network, wherein the real network complies with the constraints for the network; and
producing an actual network, using the real network and elements from a network component library to optimize the real network based on location and pipelining in order to minimize logic congestion and to optimize timing, respectively, in the actual network.