US 11,657,127 B2
Hardware intellectual property protection through provably secure state-space obfuscation
Swarup Bhunia, Gainesville, FL (US); Md Moshiur Rahman, Gainesville, FL (US); and Abdulrahman Alaql, Gainesville, FL (US)
Assigned to University of Florida Research Foundation, Inc., Gainesville, FL (US)
Filed by University of Florida Research Foundation, Inc., Gainesville, FL (US)
Filed on Dec. 14, 2020, as Appl. No. 17/120,778.
Claims priority of provisional application 62/951,494, filed on Dec. 20, 2019.
Prior Publication US 2021/0192018 A1, Jun. 24, 2021
Int. Cl. G06F 21/14 (2013.01); G06F 9/448 (2018.01); G06F 30/327 (2020.01); G06F 21/60 (2013.01); G06F 21/75 (2013.01)
CPC G06F 21/14 (2013.01) [G06F 9/4498 (2018.02); G06F 21/602 (2013.01); G06F 21/75 (2013.01); G06F 30/327 (2020.01)] 18 Claims
OG exemplary drawing
 
1. A method of protecting an integrated circuit design by locking sequential and combinational logic of the integrated circuit design, the method comprising:
obtaining, by a computing device, a gate-level netlist for the integrated circuit design, wherein functionality of the integrated circuit design is enabled by input of key inputs;
identifying, by the computing device, control path state elements that constitute a finite state machine (FSM) within the integrated circuit design and any pseudo-state elements within the gate-level netlist for the integrated circuit design, wherein the pseudo-state elements constitute data path flip-flop circuit elements that impact a state transition of the FSM, wherein the control path state elements comprise flip-flop circuit elements having a feedback path;
adding, by the computing device, one or more extra FSM elements using a multiplexer to an input of individual ones of a plurality of target elements of the integrated circuit design in parallel with original design logic at the input of the target element, wherein the plurality of target elements constitute the identified control path state elements and pseudo-state elements, wherein the one or more extra FSM elements are driven by an output of an obfuscation finite state machine that accepts a subset of the key inputs to facilitate a normal mode of operation for the integrated circuit design, wherein an input of incorrect keys that do not correspond to the subset of the key inputs cause a corruption of functionality of the integrated circuit design;
adding, by the computing device, a dummy finite state machine to implement the corruption of the functionality of the integrated circuit design, wherein input values to the dummy finite state machine correspond to a subset of the key inputs;
adding, by the computing device, modification cells to combinational logic of the integrated circuit design that are driven by an output of the dummy finite state machine and are configured to act as buffers when correct key inputs are applied to the dummy finite state machine and to corrupt the functionality of the integrated circuit design when incorrect key inputs are applied to the dummy finite state machine; and
generating, by the computing device, an obfuscated gate-level netlist of the integrated circuit design after completion of the adding operations.