US 11,657,015 B2
Multiple uplink port devices
Debendra Das Sharma, Saratoga, CA (US); Anil Vasudevan, Portland, OR (US); and David Harriman, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 20, 2021, as Appl. No. 17/153,751.
Application 17/153,751 is a continuation of application No. 16/706,637, filed on Dec. 6, 2019, abandoned.
Application 16/706,637 is a continuation of application No. 15/200,260, filed on Jul. 1, 2016, granted, now 10,503,684, issued on Dec. 10, 2019.
Prior Publication US 2021/0165756 A1, Jun. 3, 2021
Int. Cl. G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/4282 (2013.01) [G06F 13/4072 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a network adapter comprising:
a first Peripheral Component Interconnect Express (PCIe) port, wherein the first PCIe port comprises first protocol circuitry to implement a first multi-lane link compliant with a PCIe-based protocol, the first multi-lane link comprises a number of lanes, and the number of lanes comprises at least eight lanes; and
a second PCIe port, wherein the second PCIe port comprises second protocol circuitry to implement a second multi-lane link compliant with the PCIe-based protocol and the second multi-lane link comprises at least eight lanes, wherein the first and second PCIe ports are to connect the network adapter to one or more computing devices, the first PCIe port connects the network adapter to a first processor socket of the one or more computing devices via the first multi-lane link, and the second PCIe port connects the network adapter to a second processor socket of the one or more computing devices via the second multi-lane link; and
network interface controller (NIC) circuitry to determine whether data from a network is to be sent on the first PCIe port or the second PCIe port based on attributes of the data to reduce traffic from the network across an internal bus coupling the first processor socket with the second processor socket.