US 11,657,009 B2
Bidirectional interface configuration for memory
Glen E. Hush, Boise, ID (US); Richard C. Murphy, Boise, ID (US); and Honglin Sun, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 23, 2021, as Appl. No. 17/483,399.
Application 17/483,399 is a continuation of application No. 16/866,689, filed on May 5, 2020, granted, now 11,144,482.
Prior Publication US 2022/0012193 A1, Jan. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); H04L 69/323 (2022.01); H04L 12/40 (2006.01); H04B 1/38 (2015.01)
CPC G06F 13/1668 (2013.01) [H04B 1/38 (2013.01); H04L 12/40 (2013.01); H04L 69/323 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a host configured to provide set commands;
a memory sub-system coupled to the host and configured to:
cause a memory device to be operated according to a first interface protocol in a first mode in response to implementing a first set command, wherein according to the first interface protocol a particular one of a plurality of transceivers operates unidirectionally; and
cause the memory device to be operated according to a second interface protocol in a second mode in response to implementing a second set command, wherein according to the second interface protocol, the particular transceiver operates bidirectionally and the first interface protocol is noncompliant with the second interface protocol.