US 11,657,003 B2
Apparatus and method
Ilias Vougioukas, Cambridge (GB); Nikos Nikoleris, London (GB); Andreas Lars Sandberg, Cambridge (GB); and Stephan Diestelhorst, Cambridge (GB)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Jan. 31, 2020, as Appl. No. 16/778,040.
Claims priority of application No. 19386010 (EP), filed on Mar. 12, 2019.
Prior Publication US 2020/0293457 A1, Sep. 17, 2020
Int. Cl. G06F 12/10 (2016.01); G06F 12/1036 (2016.01); G06F 12/1027 (2016.01); G06N 5/04 (2023.01); G06F 9/48 (2006.01)
CPC G06F 12/1036 (2013.01) [G06F 9/4806 (2013.01); G06F 12/1027 (2013.01); G06N 5/04 (2013.01); G06F 2212/681 (2013.01)] 17 Claims
OG exemplary drawing
 
1. Apparatus comprising:
two or more processing devices each having a translation lookaside buffer to store translation data defining address translations between virtual and physical memory addresses, each address translation being associated with a respective virtual address space, wherein:
the translation lookaside buffer of a first processing device is more closely associated with the first processing device than a second, different, processing device; and
the translation lookaside buffer of the second processing device is more closely associated with the second processing device than the first processing device, and
control circuitry to:
control a direct transfer of at least a subset of the translation data from the translation lookaside buffer of the first processing device directly to the translation lookaside buffer of the second processing device; and
control the direct transfer of at least the subset of the translation data in response to initiation of execution by the second, different processing device of a processing task in a virtual address space, the virtual address space being associated with a given processing task executed by the first processing device prior to the transfer,
wherein the processing task executed by the second, different processing device is a migration of the given processing task executed by the first processing device or is a child task of the given processing task executed by the first processing device.