US 11,656,987 B2
Dynamic chunk size adjustment for cache-aware load balancing
Rimpesh Patel, Bangalore (IN); Amit Pundalik Anchi, Bangalore (IN); and Sanjib Mallick, Bangalore (IN)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by Dell Products L.P., Round Rock, TX (US)
Filed on Oct. 18, 2021, as Appl. No. 17/503,562.
Prior Publication US 2023/0120010 A1, Apr. 20, 2023
Int. Cl. G06F 12/0802 (2016.01); G06F 3/06 (2006.01)
CPC G06F 12/0802 (2013.01) [G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 2212/72 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one processing device comprising a processor coupled to a memory;
wherein the at least one processing device is configured:
to separate logical block addresses of one or more storage devices of a storage system into a plurality of ranges of logical block addresses using a designated chunk size, the chunk size denoting a particular number of logical block addresses;
to assign different ones of the ranges of logical block addresses to different ones of a plurality of cache entities of the storage system;
to select paths for delivery of respective input-output operations from a host device to the storage system based at least in part on the assigning;
to detect particular ones of the input-output operations that each overlap with two or more adjacent ranges of the plurality of ranges; and
responsive to the detected input-output operations exceeding a threshold, to modify the chunk size and to repeat at least portions of the separating, assigning, selecting and detecting utilizing the modified chunk size.