US 11,656,979 B2
Data tiering in heterogeneous memory system
Miseon Han, San Jose, CA (US); Hyung Jin Lim, San Jose, CA (US); Jongryool Kim, San Jose, CA (US); and Myeong Joon Kang, San Jose, CA (US)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 22, 2021, as Appl. No. 17/559,962.
Claims priority of provisional application 63/129,087, filed on Dec. 22, 2020.
Prior Publication US 2022/0197787 A1, Jun. 23, 2022
Int. Cl. G06F 12/02 (2006.01); G06F 12/0815 (2016.01)
CPC G06F 12/0223 (2013.01) [G06F 12/0815 (2013.01); G06F 2212/604 (2013.01); G06F 2212/608 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory device including a first memory supporting a first speed and a first capacity, and a second memory supporting a second speed slower than the first speed and a second capacity greater than the first capacity; and
a controller including a cache, and coupled to the memory device and configured to:
determine whether a miss of the cache occurs;
determine whether a target address associated with the miss of the cache exists in a set Bloom filter; and
when it is determined that the target address did not exist in the Bloom filter, identify the target address as one of memory access addresses among a plurality of addresses for memory regions of the memory device;
track, for a set period, a number of memory accesses for each of the memory access addresses;
classify each of the memory access addresses into a frequently accessed address or a normal accessed address based on the number of memory accesses in the set period; and
allocate the first memory for frequently accessed data associated with the frequently accessed address and allocate the second memory for normal data associated with the normal accessed address.