US 11,656,958 B2
Redundancy data bus inversion sharing
Liron Mula, Ramat Gan (IL); Gil Levy, Hod Hasharon (IL); and Itamar Rabenstein, Petach Tikva (IL)
Assigned to MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed by MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed on Apr. 29, 2021, as Appl. No. 17/244,539.
Prior Publication US 2022/0350713 A1, Nov. 3, 2022
Int. Cl. G06F 11/20 (2006.01); G06F 9/50 (2006.01); G06F 13/20 (2006.01)
CPC G06F 11/2007 (2013.01) [G06F 9/5011 (2013.01); G06F 13/20 (2013.01); G06F 2201/85 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a data bus;
a processor; and
memory in electronic communication with the processor; and
instructions stored in the memory, the instructions being executable by the processor to:
identify a group of channels included in the data bus;
determine whether the group of channels satisfies a criterion;
allocate at least one overhead channel to the group of channels for a set of redundancy operations or a set of data bus inversion operations based at least in part on the determining, wherein the at least one overhead channel is included in the data bus; and
encode data associated with the group of channels based at least in part on the allocating.