US 11,656,945 B2
Method and apparatus to support instruction replay for executing idempotent code in dependent processing in memory devices
John Kalamatianos, Boxborough, MA (US); Nuwan Jayasena, Santa Clara, CA (US); Sudhanva Gurumurthi, Austin, TX (US); Shaizeen Aga, Santa Clara, CA (US); and Shrikanth Ganapathy, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 24, 2020, as Appl. No. 17/133,843.
Prior Publication US 2022/0206899 A1, Jun. 30, 2022
Int. Cl. G06F 11/14 (2006.01); G06F 9/38 (2018.01)
CPC G06F 11/141 (2013.01) [G06F 9/3877 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An error protection method comprising:
issuing, by a processor, an idempotent instruction, for execution at a processing in memory (PIM) device;
maintaining the idempotent instruction in local memory until a predetermined latency period expires from when the idempotent instruction is issued; and
in response to execution of the idempotent instruction at the PIM device resulting in an error and the predetermined latency period expiring, reissuing the idempotent instruction to the PIM device.