US 11,656,935 B2
Semiconductor memory devices and memory systems
Sanguhn Cha, Suwon-si (KR); Hoyoung Song, Hwaseong-si (KR); Myungkyu Lee, Seoul (KR); and Sunghye Cho, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 18, 2021, as Appl. No. 17/351,619.
Application 17/351,619 is a continuation of application No. 16/792,515, filed on Feb. 17, 2020, granted, now 11,068,340.
Claims priority of application No. 10-2019-0072725 (KR), filed on Jun. 19, 2019.
Prior Publication US 2021/0311820 A1, Oct. 7, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/00 (2006.01); G06F 11/10 (2006.01); G06F 11/07 (2006.01); G11C 11/408 (2006.01); G06F 12/0882 (2016.01); G06F 13/16 (2006.01); G11C 11/406 (2006.01); G06F 11/30 (2006.01)
CPC G06F 11/106 (2013.01) [G06F 11/076 (2013.01); G06F 11/0772 (2013.01); G06F 11/1068 (2013.01); G06F 11/3037 (2013.01); G06F 12/0882 (2013.01); G06F 13/1673 (2013.01); G11C 11/4082 (2013.01); G11C 11/40615 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory controller; and
a semiconductor memory device coupled to the memory controller, the semiconductor memory device including
a memory cell array including a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of dynamic memory cells,
an error correction code (ECC) engine circuit,
an error information register, and
a control logic circuit configured to control the ECC engine circuit to
generate an error generation signal based on a first ECC operation on a first sub-page of a first memory cell row among the plurality of memory cell rows,
record error information in the error information register based on the error generation signal,
control the ECC engine circuit to skip an ECC encoding operation and an ECC decoding operation on the first sub-page of the first memory cell row based on the error information while performing a read operation on the first sub-page of the first memory cell row, and
transmit the error information while performing the read operation on the first sub-page of the first memory cell row to the memory controller,
wherein the memory controller performs a memory cell replacement operation in which replacing at least a portion of the first sub-page of the first memory cell row with redundancy memory cells.