US 11,656,929 B2
Memory module and operating method
Mi Jin Lee, Seoul (KR); Dong-Yoon Kim, Hwaseong-si (KR); Min-Hyouk Kim, Hwaseong-si (KR); Sung-Joon Kim, Hwaseong-si (KR); Sung Up Moon, Seoul (KR); and Jong Young Lee, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 11, 2021, as Appl. No. 17/345,276.
Claims priority of application No. 10-2020-0145259 (KR), filed on Nov. 3, 2020.
Prior Publication US 2022/0138049 A1, May 5, 2022
Int. Cl. G06F 11/07 (2006.01)
CPC G06F 11/0778 (2013.01) [G06F 11/073 (2013.01); G06F 11/0772 (2013.01); G06F 11/0784 (2013.01); G06F 11/0787 (2013.01); G06F 11/0793 (2013.01)] 18 Claims
OG exemplary drawing
1. A memory module comprising:
dynamic random access memories (DRAMs);
a controller, wherein the controller controls operation of the DRAMs; and
an active device circuit that, in response to detection of an error occurring in relation to at least one of the DRAMs, generates an interrupt and stores error information corresponding to the error,
the error information comprising an error log received responsive to the interrupt,
the active device circuit comprising
an active controller, wherein the active controller communicates the interrupt to a Central Processing Unit (CPU) including a register, and
a nonvolatile memory configured to receive the error log stored in the register, and store the error log as the error information.