US 11,656,916 B2
High-performance input-output devices supporting scalable virtualization
Utkarsh Y. Kakaiya, Folsom, CA (US); Rajesh Sankaran, Portland, OR (US); Sanjay Kumar, Hillsboro, OR (US); Kun Tian, Shanghai (CN); and Philip Lantz, Cornelius, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 29, 2021, as Appl. No. 17/361,932.
Application 17/361,932 is a continuation of application No. 16/351,396, filed on Mar. 12, 2019, granted, now 11,055,147.
Application 16/351,396 is a continuation of application No. 15/584,979, filed on May 2, 2017, granted, now 10,228,981, issued on Mar. 12, 2019.
Prior Publication US 2022/0027207 A1, Jan. 27, 2022
Int. Cl. G06F 9/50 (2006.01); G06F 15/76 (2006.01); H04L 51/226 (2022.01); G06F 15/17 (2006.01); H04L 67/2885 (2022.01); H04L 61/59 (2022.01)
CPC G06F 9/5077 (2013.01) [G06F 9/5038 (2013.01); G06F 15/76 (2013.01); H04L 51/226 (2022.05); G06F 15/17 (2013.01); H04L 61/59 (2022.05); H04L 67/2885 (2013.01); H04T 2001/2093 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of backend resources; and
one or more physical function base address registers (PF-BARs) to store one or more base addresses of one or more address ranges to be mapped to a plurality of memory-mapped input/output (MMIO) registers, including a first MMIO register to be accessed for a direct-path operation and a second MMIO register to be accessed for an intercepted-path operation; wherein hardware is to provide guest physical address to host physical address translation for the first MMIO register but not for the second MMIO register;
access for the direct-path operation is to be mapped by a virtual machine monitor (VMM) to an interface for a virtual device, the interface to be composed of one or more of the plurality of backend resources and to be identified by a process address-space identifier (PASID); and
access for the intercepted-path operation is to be intercepted by the VMM for emulation.