US 11,656,877 B2
Wavefront selection and execution
Maxim V. Kazakov, San Diego, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Mar. 31, 2021, as Appl. No. 17/219,775.
Prior Publication US 2022/0318021 A1, Oct. 6, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3885 (2013.01) [G06F 9/30152 (2013.01); G06F 9/3851 (2013.01); G06F 9/3869 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method, comprising:
at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane, wherein identifying that sufficient processing resources exist includes determining that one instruction of the first set of instructions comprises a complex instruction for which one copy of functional units exist in the processing lane and another instruction of the first set of instructions comprises a simple instruction for which multiple copies of functional units exist in the processing lane;
in response to the first identifying, executing the first set of instructions together;
at a second time for issuing instructions for execution, performing second identifying, including identifying that no instructions are available for which sufficient processing resources exist for execution together within the processing lane;
in response to the second identifying, executing an instruction independently of any other instruction.