US 11,656,875 B2
Method and system for instruction block to execution unit grouping
Mohammad Abdallah, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 14, 2020, as Appl. No. 16/928,970.
Application 16/928,970 is a continuation of application No. 15/408,323, filed on Jan. 17, 2017, abandoned.
Application 15/408,323 is a continuation of application No. 14/213,730, filed on Mar. 14, 2014, granted, now 9,823,930, issued on Nov. 21, 2017.
Claims priority of provisional application 61/800,487, filed on Mar. 15, 2013.
Prior Publication US 2020/0341768 A1, Oct. 29, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3838 (2013.01) [G06F 9/3005 (2013.01); G06F 9/3012 (2013.01); G06F 9/30094 (2013.01); G06F 9/30145 (2013.01); G06F 9/30174 (2013.01); G06F 9/384 (2013.01); G06F 9/3814 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 9/3863 (2013.01); G06F 9/3893 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of a processor, comprising:
grouping an incoming instruction sequence to form instruction blocks, wherein each of the instruction blocks comprises two half blocks;
dispatching the two half blocks of an instruction block independently or together as one instruction block to an execution unit based on dependency resolution between the two half blocks; and
executing the instructions by at least one execution unit.