US 11,656,874 B2
Asymmetrical processor memory architecture
Malcolm Douglas Stewart, Ottawa (CA); Daniel Claude Laroche, Kemptville (CA); Trevor Graydon Burton, Gloucester (CA); and Ali Osman Ors, Ottawa (CA)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP Canada Inc., Toronto (CA)
Filed on Oct. 8, 2015, as Appl. No. 14/878,474.
Claims priority of provisional application 62/061,335, filed on Oct. 8, 2014.
Prior Publication US 2016/0103784 A1, Apr. 14, 2016
Int. Cl. G06F 9/30 (2018.01); G06F 15/80 (2006.01)
CPC G06F 9/30196 (2013.01) [G06F 9/3004 (2013.01); G06F 9/30036 (2013.01); G06F 15/8061 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An asymmetrical processing system comprising:
a scalar unit having a single memory port;
a vector unit comprised of one or more computational units coupled with a vector memory space;
wherein the vector memory space includes a first memory port coupled to exchange data with the memory port of the scalar unit, and a second memory port coupled to exchange data with the computational units;
a data memory space having a memory port and contiguous with the vector memory space;
wherein the memory port of the data memory space is coupled to exchange data with the memory port of the scalar unit; and
wherein the scalar unit is configured to directly address and exchange data with both the data memory space and the vector memory space through the single memory port of the scalar unit.