US 11,656,873 B2
Shadow stack ISA extensions to support fast return and event delivery (FRED) architecture
Vedvyas Shanbhogue, Austin, TX (US); Gilbert Neiger, Portland, OR (US); Deepak K. Gupta, Portland, OR (US); and H. Peter Anvin, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 1, 2022, as Appl. No. 17/590,648.
Application 17/590,648 is a continuation of application No. 16/833,599, filed on Mar. 28, 2020, granted, now 11,243,769.
Prior Publication US 2022/0171625 A1, Jun. 2, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 21/52 (2013.01)
CPC G06F 9/30134 (2013.01) [G06F 9/30116 (2013.01); G06F 21/52 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a plurality of fast return and event delivery (FRED) shadow stack pointer (SSP) registers that store shadow stack pointers (SSPs); and
circuitry to, responsive to receipt of an event associated with an event level,
select a SSP from a FRED SSP register within the plurality of FRED SSP registers for the event level to check a shadow stack for a token,
determine whether the FRED SSP register has been verified,
when the FRED SSP register has not been verified,
read from an address specified by the SSP and lock the address read,
verify that a value read from the address specified by the SSP matches that of the shadow stack, and
upon verification, release the address and indicate the token as busy.