US 11,656,846 B2
Multiply-accumulate “0” data gating
Yaniv Fais, Tel Aviv (IL); Tomer Bar-On, Petah Tikva (IL); Jacob Subag, Kiryat Haim (IL); Jeremie Dreyfuss, Tel-Aviv (IL); Lev Faivishevsky, Kfar Saba (IL); Michael Behar, Zichron Yaakov (IL); Amit Bleiweiss, Yad binyamin (IL); Guy Jacob, Netanya (IL); Gal Leibovich, Kiryat Yam (IL); Itamar Ben-Ari, Givat HaShlosha (IL); Galina Ryvchin, Haifa (IL); and Eyal Yaacoby, Haifa (IL)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 24, 2020, as Appl. No. 17/103,179.
Application 17/103,179 is a continuation of application No. 16/833,128, filed on Mar. 27, 2020, granted, now 10,853,035.
Application 16/833,128 is a continuation of application No. 16/439,174, filed on Jun. 12, 2019, granted, now 10,606,559, issued on Mar. 31, 2020.
Application 16/439,174 is a continuation of application No. 15/499,893, filed on Apr. 28, 2017, granted, now 10,372,416, issued on Aug. 6, 2019.
Prior Publication US 2021/0141604 A1, May 13, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 7/533 (2006.01); G06N 20/00 (2019.01); G06T 1/20 (2006.01)
CPC G06F 7/5332 (2013.01) [G06N 20/00 (2019.01); G06T 1/20 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an instruction cache to receive graphics processing instructions;
a general-purpose graphics processing compute block comprising a plurality of graphics processing cores to perform operations to execute the graphics processing instructions; and
processing circuitry to:
receive, into at least one of a multiply unit or an accumulate unit, a first operand and a second operand from a layer of a convolutional neural network, wherein the first operand and the second operand comprise at least one of inference weights or activations of the convolutional neural network; and
responsive to at least one of the first operand or the second operand having a value of negative one, cause the second operand to be negative and bypass the multiply unit, such that the multiply unit performs no operations on the first operand or the second operand.