US 11,656,772 B2
Memory controller and storage device including the same
Hongseok Kim, Seoul (KR); Sang Hyun Park, Hwaseong-si (KR); Sunggil Hong, Seoul (KR); Hayoung Lim, Seoul (KR); and EHyun Nam, Seoul (KR)
Assigned to FADU Inc., Seoul (KR)
Filed by FADU Inc., Seoul (KR)
Filed on Jun. 28, 2021, as Appl. No. 17/359,935.
Claims priority of provisional application 63/046,780, filed on Jul. 1, 2020.
Claims priority of application No. 10-2020-0080803 (KR), filed on Jul. 1, 2020.
Prior Publication US 2022/0004326 A1, Jan. 6, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0619 (2013.01); G06F 3/0623 (2013.01); G06F 3/0659 (2013.01); G06F 3/0661 (2013.01); G06F 3/0679 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a scrambler configured to generate at least two scrambled data, having different bit values, by randomizing, in different manners, original data received from a host;
a toggle counter configured to count the numbers of toggles per bit of the at least two scrambled data generated by the scrambler; and
a scrambled data output unit configured to compare the counted numbers of toggles of the at least two scrambled data with each other and output one scrambled data with a smallest number of toggles among the at least two scrambled data,
wherein the one scrambled data output from the scrambled data output unit is programmed in a non-volatile memory device, and
wherein the toggles are changes between sequential bits in the at least two scrambled data.