US 11,656,765 B2
DBI circuit and memory device including the same
Yong Sang Park, Gyeonggi-do (KR); Dae Woo Kim, Gyeonggi-do (KR); Min Soo Lim, Gyeonggi-do (KR); and Young Duke Seo, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jun. 21, 2021, as Appl. No. 17/353,287.
Claims priority of application No. 10-2021-0001773 (KR), filed on Jan. 7, 2021.
Prior Publication US 2022/0214804 A1, Jul. 7, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 37 Claims
OG exemplary drawing
 
1. A data bus inversion (DBI) circuit of a memory device, comprising:
a first processing circuit configured to generate first combination data by combining read data read from a memory cell region and previous data previously outputted from a data line, and generate second combination data by selectively inverting the first combination data depending on a result of comparing the first combination data and the previous data; and
a second processing circuit configured to generate data to be outputted from the data line, by combining the second combination data and the previous data,
wherein the second processing circuit generates bits of unnecessary bit positions in the data to be the same as bits of the unnecessary bit positions in the previous data,
wherein the first processing circuit determines a reference number corresponding to the number of necessary bits in the data, determines the number of transitions by comparing the first combination data with the previous data, and generates the second combination data by selectively inverting the first combination data based on the number of transitions and the reference number.