US 11,656,673 B2
Managing reduced power memory operations
Qing Liang, Boise, ID (US); Jonathan Scott Parry, Boise, ID (US); David Aaron Palmer, Boise, ID (US); and Stephen Hanna, Fort Collins, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 29, 2020, as Appl. No. 17/136,891.
Claims priority of provisional application 62/955,038, filed on Dec. 30, 2019.
Prior Publication US 2021/0200299 A1, Jul. 1, 2021
Int. Cl. G06F 1/3234 (2019.01); G06F 3/06 (2006.01)
CPC G06F 1/3275 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0658 (2013.01); G06F 3/0679 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory device comprising:
a NAND memory array; and
a memory controller configured to receive commands from a host device, the memory controller including processing circuitry including one or more processors, and is configured to perform operations including:
initiating a first NAND memory management operation in the memory array, the NAND memory operation including at least one of programming a portion of the NAND memory array, erasing a portion of the NAND memory array, and reading from the NAND memory array;
after initiating the first NAND memory management operation, determining whether another memory operation is pending;
on determining that no other memory operation is pending, placing at least one component of the memory controller in a lower power mode during the first NAND memory management operation;
setting a wakeup time based on a predicted completion time of the first NAND memory management operation, including,
receiving a predicted completion time of the first memory management operation from an interface in communication with the memory array; and
based on the predicted completion time of the first memory management operation, entering a selected power saving mode; and
toggling the at least one component of the memory controller out of the lower power mode upon the first to occur of a wake event and expiration of the wakeup time.