US 11,656,186 B2
Wafer and method for analyzing shape thereof
Chung Hyun Lee, Seoul (KR)
Assigned to SK SILTRON CO., LTD., Gyeongsangbuk-Do (KR)
Filed by SK Siltron Co., LTD., Gyeongsangbuk-do (KR)
Filed on Oct. 13, 2020, as Appl. No. 17/69,179.
Claims priority of application No. 10-2020-0088216 (KR), filed on Jul. 16, 2020.
Prior Publication US 2022/0018788 A1, Jan. 20, 2022
Int. Cl. G01N 21/95 (2006.01); G01B 11/24 (2006.01); G06T 7/00 (2017.01); H01L 21/66 (2006.01)
CPC G01N 21/9501 (2013.01) [G01B 11/24 (2013.01); G06T 7/0006 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01); G06T 2207/30148 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A wafer comprising:
a bulk region;
a front side and a back side of the bulk region configured to face each other in parallel; and
an edge region disposed at an edge of the bulk region,
wherein the edge region comprises a bevel portion and an apex disposed at an edge thereof, wherein:
the bevel portion comprises a first point having a maximum curvature and a second point spaced apart from the first point in a direction towards the apex, the first point and the second point configured to be sequentially disposed in a direction towards the apex from the front side; and
a height difference between the first point and the second point is proportional to a second-order differential value of location coordinates on a surface of the wafer at the first point.