US 12,310,251 B2
Magnetoresistance memory device and method of manufacturing magnetoresistance memory device
Takao Ochiai, Seoul (KR); Kenichi Yoshino, Seongnam-si (KR); Kazuya Sawada, Seoul (KR); and Naoki Akiyama, Seoul (KR)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 10, 2021, as Appl. No. 17/471,327.
Claims priority of application No. 2020-157296 (JP), filed on Sep. 18, 2020.
Prior Publication US 2022/0093847 A1, Mar. 24, 2022
Int. Cl. H10N 50/80 (2023.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01)
CPC H10N 50/80 (2023.02) [G11C 11/161 (2013.01); H10B 61/10 (2023.02); H10N 50/01 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A magnetoresistance memory device comprising:
a first conductor;
a silicon oxide on the first conductor, the silicon oxide including a dopant and having a first part on the first conductor and a second part adjacent to the first part on the first conductor, the second part being higher than the first part, a concentration of the dopant of the second part being higher than a concentration of the dopant of the first part;
a second conductor on the second part of the silicon oxide; and
a first layer stack on the second conductor, the first layer stack including a first magnetic layer, a second magnetic layer, and a first insulating layer between the first magnetic layer and the second magnetic layer.