| CPC H10K 59/1213 (2023.02) [H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/131 (2023.02); H10K 71/00 (2023.02)] | 20 Claims |
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1. A transistor display panel comprising:
a substrate;
a lower electrode disposed on the substrate;
a buffer layer disposed on the lower electrode;
a transistor disposed on the substrate; and
a pixel electrode electrically connected to the transistor,
wherein the transistor includes:
a semiconductor layer disposed on the substrate;
a gate electrode overlapping a part of the semiconductor layer; and
a first electrode and a second electrode disposed on the gate electrode,
wherein the lower electrode is electrically connected to the pixel electrode, and
wherein the lower electrode is disposed between the substrate and the transistor along a thickness direction of the substrate.
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