US 12,310,159 B2
Integrated structure for an optoelectronic device and method of fabricating the same
Yijing Chen, Singapore (SG); Li Zhang, Singapore (SG); Kenneth Eng Kian Lee, Singapore (SG); and Eugene A. Fitzgerald, Singapore (SG)
Assigned to MASSACHUSETTS INSTITUTE OF TECHNOLOGY, Cambridge, MA (US)
Appl. No. 17/622,097
Filed by MASSACHUSETTS INSTITUTE OF TECHNOLOGY, Cambridge, MA (US)
PCT Filed Jun. 24, 2020, PCT No. PCT/SG2020/050357
§ 371(c)(1), (2) Date Dec. 22, 2021,
PCT Pub. No. WO2020/263183, PCT Pub. Date Dec. 30, 2020.
Claims priority of application No. 10201906072T (SG), filed on Jun. 28, 2019.
Prior Publication US 2022/0246670 A1, Aug. 4, 2022
Int. Cl. H10H 29/10 (2025.01); H10H 20/01 (2025.01); H10H 20/855 (2025.01); H10H 20/856 (2025.01); H10H 20/80 (2025.01)
CPC H10H 29/10 (2025.01) [H10H 20/01 (2025.01); H10H 20/855 (2025.01); H10H 20/856 (2025.01); H10H 20/0363 (2025.01); H10H 20/872 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated structure for an optoelectronic device, the integrated structure comprising:
a complementary metal-oxide-semiconductor, CMOS, backplane comprising a driver circuit for the optoelectronic device;
a plurality of optical elements on the CMOS backplane, wherein the plurality of optical elements are based on a material system different from CMOS and are disposed in different device layers, each optical element comprising of a light emitting layer disposed between top and bottom contact layers;
a first bonding dielectric provided between the CMOS backplane and a first one of the different device layers for monolithic integration; and
a second bonding dielectric provided between respective ones of the different device layers for monolithic integration, the second bonding dielectric being transparent;
wherein, for each of the device layers, the driver circuit is connected to the optical element in the device layer via a vertical interconnect formed in a dielectric material of the device layer, wherein the vertical interconnect is connected to a surface of one of the top and bottom contact layers, said surface facing away from the CMOS backplane; and/or
wherein the integrated structure comprises one or more redundant tungsten plugs to prevent crosstalk between adjacent optical elements.