US 12,310,132 B2
Semiconductor package, semiconductor package manufacturing method, and electronic device
Mitsuhito Kanatake, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/608,803
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Feb. 26, 2020, PCT No. PCT/JP2020/007661
§ 371(c)(1), (2) Date Nov. 4, 2021,
PCT Pub. No. WO2020/230404, PCT Pub. Date Nov. 19, 2020.
Claims priority of application No. 2019-092102 (JP), filed on May 15, 2019.
Prior Publication US 2022/0254824 A1, Aug. 11, 2022
Int. Cl. H10F 39/00 (2025.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01)
CPC H10F 39/804 (2025.01) [H01L 21/56 (2013.01); H01L 24/48 (2013.01); H10F 39/811 (2025.01); H01L 2224/48228 (2013.01); H01L 2224/48453 (2013.01); H01L 2224/48463 (2013.01); H01L 2924/182 (2013.01); H01L 2924/18301 (2013.01); H01L 2924/186 (2013.01); H10F 39/809 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate;
a semiconductor chip on the substrate, wherein the semiconductor chip includes a chip plane;
a plurality of wires;
a first plurality of bumps on the chip plane, wherein
each of the first plurality of bumps has a first height from the chip plane, and
each of the first plurality of bumps is connected to the substrate via the plurality of wires;
a protective material including:
an upper surface on which light is incident; and
a lower surface opposite to the upper surface, wherein the lower surface includes a recess; and
a support, including an end, on the chip plane, wherein
the support is configured to support the protective material,
the end is in the recess,
the support has a second height from the chip plane, and
the second height is higher than the first height.