US 12,310,127 B2
Image sensor including a transistor with a vertical channel and a method of manufacturing the same
Wonseok Lee, Suwon-si (KR); and Eunsub Shim, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 13, 2022, as Appl. No. 17/743,788.
Claims priority of application No. 10-2021-0070967 (KR), filed on Jun. 1, 2021; and application No. 10-2021-0108178 (KR), filed on Aug. 17, 2021.
Prior Publication US 2022/0384512 A1, Dec. 1, 2022
Int. Cl. H01L 27/146 (2006.01); H10F 39/00 (2025.01); H10F 39/18 (2025.01)
CPC H10F 39/18 (2025.01) [H10F 39/014 (2025.01); H10F 39/802 (2025.01); H10F 39/8037 (2025.01); H10F 39/805 (2025.01); H10F 39/807 (2025.01); H10F 39/811 (2025.01)] 19 Claims
OG exemplary drawing
 
1. An image sensor, comprising:
photodiodes arranged in a substrate;
active pillars connected to the photodiodes and extending in a vertical direction perpendicular to a bottom surface of the substrate;
at least two transistors stacked in the vertical direction, wherein portions of the active pillars are channel areas of the at least two transistors;
a floating diffusion (FD) area disposed under a transfer transistor, which is one of the at least two transistors, wherein the FD area is configured to receive charge from the photodiode through the transfer transistor and the portions of the active pillars; and
a light transmitting layer disposed on a top surface of the substrate,
wherein the photodiodes, the at least two transistors, the FD area, and the light transmitting layer are formed on a first semiconductor chip, and
the image sensor further comprises a second semiconductor chip coupled to a bottom surface of the first semiconductor chip and including logic elements.