US 12,310,117 B2
Semiconductor device
Kwan Yeob Chae, Seoul (KR); and San Kang, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 11, 2021, as Appl. No. 17/498,330.
Claims priority of application No. 10-2021-0032595 (KR), filed on Mar. 12, 2021.
Prior Publication US 2022/0293584 A1, Sep. 15, 2022
Int. Cl. H10D 89/60 (2025.01); H03K 19/0185 (2006.01); H03K 19/17736 (2020.01)
CPC H10D 89/611 (2025.01) [H03K 19/0185 (2013.01); H03K 19/17744 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first wiring that receives an input signal and extends in a first direction;
a first gate wiring that extends in a second direction that intersects the first direction;
a first impurity region disposed in a first active region on one side of the first gate wiring and is connected to the first wiring;
a second impurity region disposed in the first active region on an other side of the first gate wiring and is connected to the first wiring, wherein the second impurity region is spaced apart from the first impurity region in the first direction;
a second gate wiring that extends in the second direction and spaced apart from the first gate wiring in the first direction, and connected to the first wiring;
a first inverter that includes the second gate wiring and is connected to the first wiring through which the first inverter receives the input signal;
a second wiring that extends in the second direction, is disposed higher than the first wiring, and is connected to the first wiring; and
a third wiring that extends in the first direction, is disposed lower than the second wiring, and is connected to the second wiring,
wherein the first and second impurity regions are connected to the third wiring.