US 12,310,114 B2
Display panel and display device
Qingjun Lai, Xiamen (CN); Yihua Zhu, Xiamen (CN); Yong Yuan, Xiamen (CN); Ping An, Xiamen (CN); and Zhaokeng Cao, Xiamen (CN)
Assigned to Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
Filed by Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
Filed on Oct. 27, 2023, as Appl. No. 18/384,593.
Application 18/384,593 is a continuation of application No. 17/451,136, filed on Oct. 15, 2021, granted, now 11,837,606.
Claims priority of application No. 202011637184.4 (CN), filed on Dec. 31, 2020.
Prior Publication US 2024/0063226 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 19/00 (2006.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC H10D 86/60 (2025.01) [G09G 3/3266 (2013.01); G11C 19/28 (2013.01); H10D 86/423 (2025.01); G09G 2310/0286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display panel, comprising at least one driving circuit and at least one pixel circuit, wherein:
a driving circuit of the at least one driving circuit provides a driving signal for a pixel circuit of the at least one pixel circuit, the driving circuit includes N-level shift registers connected in cascade, wherein N is greater than or equal to two, and the pixel circuit provides a display signal for a display unit of the display panel;
a shift register of the N-level shift registers includes at least one first transistor, wherein the at least one first transistor includes at least one first active layer, and an active layer with a largest area among the at least one first active layer is a first preset active layer;
the pixel circuit includes at least one second transistor, the at least one second transistor includes at least one second active layer, an active layer with a largest area among active layers containing silicon of the at least one second active layer is a second preset active layer, and an active layer with a largest area among active layers containing an oxide semiconductor of the at least one second active layer is a third preset active layer; and
the first preset active layer is an active layer containing silicon, the shift register of the N-level shift registers further includes a fourth preset active layer, and an active layer with a largest area among active layers containing oxide semiconductor of the at least one first active layer is the fourth preset active layer; or the first preset active layer is an active layer containing oxide semiconductor, the shift register of the N-level shift registers further includes a fourth preset active layer, and an active layer with a largest area among active layers containing silicon of the at least one first active layer is the fourth preset active layer;
wherein a sum of an area of the first preset active layer and an area of the fourth preset active layer is greater than a sum of an area of the second preset active layer and an area of the third preset active layer.