US 12,310,108 B2
Base plate and display panel
Xiaofang Tan, Shenzhen (CN); and Zhiwei Song, Shenzhen (CN)
Assigned to SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Shenzhen (CN)
Appl. No. 17/607,317
Filed by SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Shenzhen (CN)
PCT Filed Sep. 7, 2021, PCT No. PCT/CN2021/116863
§ 371(c)(1), (2) Date Feb. 23, 2023,
PCT Pub. No. WO2023/019654, PCT Pub. Date Feb. 23, 2023.
Claims priority of application No. 202110936401.8 (CN), filed on Aug. 16, 2021.
Prior Publication US 2024/0047466 A1, Feb. 8, 2024
Int. Cl. G02F 1/1333 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC H10D 86/60 (2025.01) [G02F 1/133345 (2013.01); G02F 1/136209 (2013.01); G02F 1/1368 (2013.01); H10D 86/423 (2025.01); G02F 1/133357 (2021.01); G02F 1/136227 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A base plate, comprising:
a substrate; and
a plurality of thin film transistors, wherein the thin film transistors are arranged on the substrate;
wherein the thin film transistors comprise:
a gate electrode, wherein the gate electrode is disposed on the substrate;
an active layer, wherein the active layer is disposed on the substrate and arranged in a different layer from the gate electrode, and the active layer is arranged to overlap the gate electrode;
a barrier layer, wherein the barrier layer at least covers the active layer and the gate electrode, and the barrier layer is used to block water and oxygen;
a flat layer, wherein the flat layer covers the barrier layer; and
a source-drain metal layer, wherein the source-drain metal layer is disposed on the flat layer, the source-drain metal layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected to the active layer;
wherein the base plate further comprises a first insulating layer, the first insulating layer is disposed on the gate electrode, the active layer is disposed on the first insulating layer, and the barrier layer covers an outer surface of the active layer; and
wherein the first insulating layer is provided with a trench, the trench is provided around an outer periphery of the gate electrode, and the barrier layer covers the trench.