US 12,310,106 B2
Devices including stacked nanosheet transistors
Byounghak Hong, Albany, NY (US); Seunghyun Song, Albany, NY (US); Ki-Il Kim, Clifton Park, NY (US); Gunho Jo, Clifton Park, NY (US); and Kang-Ill Seo, Springfield, VA (US)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 1, 2023, as Appl. No. 18/499,258.
Application 18/499,258 is a division of application No. 17/380,999, filed on Jul. 20, 2021, granted, now 11,843,001.
Claims priority of provisional application 63/188,501, filed on May 14, 2021.
Prior Publication US 2024/0072060 A1, Feb. 29, 2024
Int. Cl. H01L 27/12 (2006.01); H01L 21/822 (2006.01); H01L 21/8234 (2006.01); H01L 21/84 (2006.01); H01L 27/088 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01); H10D 88/00 (2025.01)
CPC H10D 86/201 (2025.01) [H10D 84/0128 (2025.01); H10D 84/0142 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01); H10D 86/01 (2025.01); H10D 88/01 (2025.01)] 8 Claims
OG exemplary drawing
 
1. A method of forming a nanosheet transistor device, the method comprising:
forming a preliminary transistor stack comprising a first plurality of nanosheets and a second plurality of nanosheets on the first plurality of nanosheets;
forming a recess in the preliminary transistor stack by removing a first portion of the second plurality of nanosheets; and
forming a spacer in the recess,
wherein the spacer overlaps the first plurality of nanosheets in a direction and contacts a second portion of the second plurality of nanosheets that remains after removing the first portion,
wherein a lower end of the recess is at a position that is different than an upper surface of an uppermost nanosheet among the first plurality of nanosheets in the direction, and
wherein the position of the lower end of the recess is different than a lower surface of a lowermost nanosheet among the second plurality of nanosheets in the direction.