US 12,310,105 B2
Semiconductor device including high electron mobility transistors with an improved backside electrode being applied in a half-bridge circuit
Walter Wohlmuth, Taipei (TW); Shin-Cheng Lin, Hsinchu County (TW); and Chia-Ching Huang, Taoyuan (TW)
Assigned to Vanguard International Semiconductor Corporation, Hsinchu (TW)
Filed by Vanguard International Semiconductor Corporation, Hsinchu (TW)
Filed on Mar. 2, 2022, as Appl. No. 17/684,438.
Prior Publication US 2023/0282645 A1, Sep. 7, 2023
Int. Cl. H10D 86/00 (2025.01); H01L 23/02 (2006.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 64/27 (2025.01)
CPC H10D 86/201 (2025.01) [H01L 23/02 (2013.01); H10D 30/475 (2025.01); H10D 62/824 (2025.01); H10D 64/411 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an insulating layer, a semiconductor layer and a compound semiconductor stacked layer, disposed on a substrate in sequence;
a first transistor, disposed in a first device region, and comprising a first gate electrode, a first source electrode and a first drain electrode disposed on the compound semiconductor stacked layer;
a second transistor, disposed in a second device region and comprising a second gate electrode, a second source electrode and a second drain electrode disposed on the compound semiconductor stacked layer;
an isolation structure, disposed between the first transistor and the second transistor; and
a conductive structure, disposed in the second device region, passing through the compound semiconductor stacked layer, and electrically connecting the semiconductor layer to the second source electrode,
wherein there is no electrical connection between the semiconductor layer in the first device region and the first source electrode, the first source electrode is electrically connected to the second drain electrode, and the semiconductor layer in the first device region is an electrically floating layer, or is configured to be electrically connected to a ground node.