| CPC H10D 84/907 (2025.01) [H10D 89/10 (2025.01); H10D 84/912 (2025.01); H10D 84/941 (2025.01); H10D 84/961 (2025.01); H10D 84/962 (2025.01); H10D 84/964 (2025.01); H10D 84/981 (2025.01); H10D 84/985 (2025.01)] | 1 Claim |
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1. A semiconductor integrated circuit device including a first standard cell and a second standard cell placed adjacent to the first standard cell in a first direction, the first standard cell comprising:
a first power supply line extending in the first direction and supplying a first power supply voltage;
a second power supply line extending in the first direction, arranged spaced apart from the first power supply line in a second direction perpendicular to the first direction, and supplying a second power supply voltage different from the first power supply voltage;
a first transistor that is a three-dimensional transistor of a first conductivity type lying between the first power supply line and the second power supply line as viewed in a depth direction in plan, the depth direction being perpendicular to the first direction and the second direction; and
a second transistor that is a three-dimensional transistor of a second conductivity type, formed above the first transistor in the depth direction, lying between the first power supply line and the second power supply line as viewed in the depth direction in plan,
the second standard cell comprising:
a third power supply line extending in the first direction and supplying the first power supply voltage;
a fourth power supply line extending in the first direction and supplying the second power supply voltage;
a third transistor that is a three-dimensional transistor of the first conductivity type lying between the third power supply line and the fourth power supply line as viewed in the depth direction in plan; and
a fourth transistor that is a three-dimensional transistor of the second conductivity type, formed above the third transistor in the depth direction, lying between the third power supply line and the fourth power supply line as viewed in the depth direction in plan, wherein:
the first transistor and the third transistor face each other, and the second transistor and the fourth transistor face each other, across a cell boundary that is a boundary between the first standard cell and the second standard cell,
the first standard cell further comprises:
a first local interconnect extending in the second direction, connected with a source or drain of the first transistor whichever is closer to the cell boundary; and
a second local interconnect extending in the second direction and overlapping the first local interconnect as viewed in the depth direction in plan, connected with a source or drain of the second transistor whichever is closer to the cell boundary, and
the first local interconnect overlaps the first and second power supply lines as viewed in the depth direction in plan, and the second local interconnect overlaps the first and second power supply lines as viewed in the depth direction in plan.
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