US 12,310,102 B2
Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers
Tsung-Sheng Kang, Ballston Lake, NY (US); Ardasheir Rahman, Schenectady, NY (US); Tao Li, Slingerlands, NY (US); and Su Chen Fan, Cohoes, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 21, 2023, as Appl. No. 18/471,718.
Application 18/471,718 is a division of application No. 17/113,674, filed on Dec. 7, 2020, granted, now 11,810,918.
Prior Publication US 2024/0014211 A1, Jan. 11, 2024
Int. Cl. H10D 84/85 (2025.01); H03K 19/173 (2006.01); H03K 19/20 (2006.01); H10D 30/01 (2025.01); H10D 30/63 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 88/00 (2025.01); H10D 64/27 (2025.01)
CPC H10D 84/85 (2025.01) [H03K 19/173 (2013.01); H03K 19/20 (2013.01); H10D 30/025 (2025.01); H10D 30/63 (2025.01); H10D 84/0195 (2025.01); H10D 84/038 (2025.01); H10D 88/00 (2025.01); H10D 64/518 (2025.01); H10D 84/0186 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A two-input logic gate, comprising:
two two-channel n-type field-effect transistors, the two two-channel n-type field-effect transistors comprising a first vertical fin, a second vertical fin, a first bottom epitaxial layer surrounding a bottom portion of the first vertical fin and the second vertical fin, a first top epitaxial layer surrounding a top portion of the first vertical fin, a second top epitaxial layer surrounding a top portion of the second vertical fin, a first shared epitaxial layer surrounding a middle portion of the first vertical fin, and a second shared epitaxial layer surrounding a middle portion of the second vertical fin;
two two-channel p-type field-effect transistors, the two two-channel p-type field-effect transistors comprising a third vertical fin, a fourth vertical fin, a second bottom epitaxial layer surrounding a bottom portion of the third vertical fin and the fourth vertical fin, a third top epitaxial layer surrounding a top portion of the third vertical fin, a fourth top epitaxial layer surrounding a middle portion of the fourth vertical fin, a third shared epitaxial layer surrounding a middle portion of the third vertical fin, a fourth shared epitaxial layer surrounding a middle portion of the fourth vertical fin, and an interlayer dielectric layer separating the third shared epitaxial layer and the fourth shared epitaxial layer; and
a connecting layer contacting at least one of the first bottom epitaxial layer and the second bottom epitaxial layer, the connecting layer further contacting one of (i) the first top epitaxial layer and the second top epitaxial layer of the two two-channel n-type field-effect transistors and (ii) the third top epitaxial layer and the fourth top epitaxial layer of the two two-channel p-type field effect transistors.