US 12,310,101 B2
Gate dielectrics for complementary metal oxide semiconductors transistors and methods of fabrication
Ashish Verma Penumatcha, Beaverton, OR (US); Seung Hoon Sung, Portland, OR (US); Jack Kavalieros, Portland, OR (US); Uygar Avci, Portland, OR (US); Tristan Tronic, Aloha, OR (US); Shriram Shivaraman, Hillsboro, OR (US); Devin Merrill, McMinnville, OR (US); Tobias Brown-Heft, Portland, OR (US); Kirby Maxey, Hillsboro, OR (US); Matthew Metz, Portland, OR (US); and Ian Young, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/133,208.
Prior Publication US 2022/0199619 A1, Jun. 23, 2022
Int. Cl. H10D 84/85 (2025.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10D 84/85 (2025.01) [H10B 61/22 (2023.02); H10B 63/30 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 70/011 (2023.02); H10N 70/253 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A complementary metal oxide semiconductor (CMOS) structure, comprising:
a first transistor comprising:
a first gate dielectric layer above a first channel, the first gate dielectric layer comprising Hf1-xZrxO2, wherein the first gate dielectric layer has a thickness of at least 1.3 nm;
a first gate electrode coupled to the first channel through the first gate dielectric layer;
a gate dielectric layer comprising oxygen and one or more of aluminum, lanthanum or yttrium located between the first gate dielectric layer and the channel and having a thickness between 0.7 nm and 1 nm;
and
a first source region and a first drain region of a first conductivity type on opposite sides of the first gate electrode; and
a second transistor comprising:
a second gate dielectric layer above a second channel, the second gate dielectric layer comprising Hf1-xZrxO2, wherein x for the second gate dielectric layer is greater than x for the first gate dielectric layer;
a second gate electrode coupled to the second channel through the second gate dielectric layer; and
a second source region and a second drain region of a second, complementary, conductivity type on opposite sides of the second gate electrode.