US 12,310,100 B2
Dielectric reflow for boundary control
Jing Guo, Niskayuna, NY (US); Ekmini Anuja De Silva, Slingerlands, NY (US); Nicolas Loubet, Guilderland, NY (US); Indira Seshadri, Niskayuna, NY (US); Ruqiang Bao, Niskayuna, NY (US); and Nelson Felix, Slingerlands, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 30, 2021, as Appl. No. 17/537,562.
Prior Publication US 2023/0170348 A1, Jun. 1, 2023
Int. Cl. H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 84/834 (2025.01) [H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H01L 21/0262 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a first layer on a first transistor region and a second transistor region, the first and second transistor regions being adjacent;
forming a dielectric layer to protect the second transistor region such that the first transistor region is exposed, the dielectric layer bounded at a first location;
removing a portion of the first layer on the first transistor region such that the portion removed undercuts the dielectric layer and leaves a gap under the dielectric layer; and
reflowing the dielectric layer protecting the second transistor region such that at least a reflowed portion of the dielectric layer extends beyond the first location and fills in the gap.