| CPC H10D 84/038 (2025.01) [H01L 21/76224 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 64/017 (2025.01); H10D 84/0158 (2025.01); H10D 84/834 (2025.01); H10D 84/0151 (2025.01)] | 20 Claims |
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1. A method comprising:
forming first and second semiconductor fins upwardly extending from a substrate;
forming a gate strip extending across the first and second semiconductor fins;
growing first source/drain regions on the first semiconductor fin and at opposite sides of the gate strip, and second source/drain regions on the second semiconductor fin and at opposite sides of the gate strip;
depositing a dielectric layer over the first and second source/drain regions;
forming an isolation material in the dielectric layer and between one of the first source/drain regions and one of the second source/drain regions;
performing an etching process on the isolation material and the gate strip to form an opening, the opening breaking the gate strip and recessing the isolation material, wherein the etching process uses an etchant that etches the isolation material at a slower etch rate than etching the gate strip; and
forming a separation material in the opening.
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