US 12,310,094 B2
Nano-sheet-based complementary metal-oxide-semiconductor devices with asymmetric inner spacers
Bo-Feng Young, Taipei (TW); Sai-Hooi Yeong, Hsinchu County (TW); Kuan-Lun Cheng, Hsin-Chu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 6, 2022, as Appl. No. 17/858,991.
Application 17/858,991 is a division of application No. 16/875,726, filed on May 15, 2020, granted, now 11,476,166.
Claims priority of provisional application 62/880,311, filed on Jul. 30, 2019.
Prior Publication US 2022/0352036 A1, Nov. 3, 2022
Int. Cl. H10D 84/03 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0184 (2025.01); H10D 84/85 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a stack over a substrate, the stack including first semiconductor layers interleaved by second semiconductor layers;
forming a first fin-shaped structure from the stack over a first area of the substrate;
forming a second fin-shaped structure from the stack over a second area of the substrate;
forming a dummy gate stack over the first fin-shaped structure and the second fin-shaped structure;
depositing a first gate spacer layer over the substrate and the dummy gate stack;
depositing a second gate spacer layer over the first gate spacer layer;
after the depositing of the second gate spacer layer, forming a first source/drain trench over the first fin-shaped structure while the second fin-shaped structure is covered by a first mask layer;
after the forming of the first source/drain trench, forming first inner spacer features to interleave the second semiconductor layers in the first area, while the second fin-shaped structure remains covered by the first mask layer;
forming a first source/drain feature in the first source/drain trench such that the first source/drain feature is in direct contact with the first and the second gate spacer layers;
forming a first etch stop layer over the first source/drain feature;
forming a second mask layer on the first etch stop layer;
after the forming of the second mask layer, removing the first mask layer;
after the removing of the first mask layer, forming a second source/drain trench over the second fin-shaped structure while the first fin-shaped structure is covered by the second mask layer;
forming second inner spacer features to interleave the second semiconductor layers in the second area, while the first fin-shaped structure remains covered by the second mask layer;
forming a second source/drain feature in the second source/drain trench;
forming a second etch stop layer over the second source/drain feature; and
after the forming of the second etch stop layer, removing the second mask layer.